United States
Wonderschool
Meta
ASIC Engineer, Design Verification
United States
Austin, Texas, United States · Sunnyvale, California, United States
PythonC++
About the opportunity
Meta's Infrastructure Silicon team is seeking a Staff ASIC Design Verification Engineer to drive verification strategy and execution for custom silicon powering Meta's data center infrastructure. In this role, you will lead the end-to-end verification of complex IP blocks and SoCs designed for AI/ML acceleration, networking, and video processing workloads. You will architect scalable UVM-based verification environments, define coverage models, and partner with design, emulation, and post-silicon validation teams to achieve first-pass silicon success across Meta's infrastructure ASIC portfolio.
Responsibilities
- Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification
- Develop functional tests based on verification test plan
- Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage
- Debug, root-cause and resolve functional failures in the design, partnering with the Design team
- Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality
- Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry
Minimum Qualifications
- Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
- 8+ years of hands-on experience in SystemVerilog/UVM methodology and/or C/C++ based verification
- 8+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies
- Experience in one or more of the following areas along with functional verification-SV Assertions, Formal, Emulation
- Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments
- Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle
Preferred Qualifications
- Experience with compute and/or memory subsystem and/or collective functional and performance verification
- Experience with verification of ARM/RISC-V/GPU based sub-systems or SoCs
- Experience in development of UVM based verification environments from scratch
- Prior experience with fullchip or package-level integration projects
- Experience working across and building relationships with cross-functional design, model and emulation teams
- Familiarity with host and system-level concepts for functional verification
- Experience with chiplet based architectures and package-level integration verification
$178,000/year to $250,000/year + bonus + equity + benefits
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